FC 35 - Timer

The timer function code performs timing, pulsed timing, or timed out delay functions. The timing mode is specified by S2 and the duration of time delay is specified by S3. Figure 35-1 shows output shapes for each mode of operation.

 

 

Outputs:

Blk

Type

Description

N

R

Logic state defined for pulse, timing or timed out delay functions

 

 

Specifications:

Spec

Tune

Default

Type

Range

Description

S1

N

0

I

Note 1

Block address of set input

S2

N

0

I

0 - 2

0 = pulse output

1 = timed out

2 = timing

00X = normal

10X = time during start up period

NOTE: The tens digit is not used and must be set to 0

S3

Y

0.000

R

Full

Time delay in seconds

 

NOTES:

1. Maximum values are: 9,998 for the BRC-100, IMMFP11/12 and 31,998 for the HAC

 

 

35.1 Explanation

 

Pulse Output Mode

In the pulse output mode, the output becomes logic 1 whenever the input becomes logic 1. If the input returns to logic 0 before the time delay (S3) ends, the output will remain logic 1 for the entire interval. If the input remains a logic 1 after the time delay expires, the output will return to a logic 0 at the end of the time delay, and remain a logic 0 until there is another 0 to 1 transition of the input. Despite how long the input value remains in the logic 1 state, the output remains in the logic 1 state for the duration of the time delay specified in S3. The characteristic of the pulse output mode is often called one shot.

 

Timed Out Mode

In the timed out mode, the input must remain logic 1 for longer than the time delay before the output will track it. The output will remain logic 0 if the input pulse duration is shorter than the time delay, and will become logic 1 only if the input remains logic 1 for a period of time exceeding the time delay. It will then track the input.

 

Timing Mode

In the timing mode, the output tracks the input for the length of the time delay, but transitions to logic 0 at the end of the time delay, despite the input value. The output becomes a logic 1 whenever the input becomes a logic 1. If the input returns to logic 0 before the specified time delay ends, then the output also returns to logic 0. If the input remains a logic 1 after the specified time delay, the output will return to logic 0 at the end of the time delay.