FC 126 - Real Signal Demultiplexer

The real signal demultiplexer function code outputs boolean signals based on a real input value. The real value can be converted to boolean values in three modes (select, integer and BCD). An unlimited number of real signal demultiplexer blocks may be linked together in the select mode (demultiplex the real input into the required number of boolean outputs). Up to four blocks may be linked together in the integer and BCD modes for demultiplexing. The first block in the link list is the group master. The master accepts the input signal and drives the outputs for the group.

 

 

Outputs:

Blk

Type

Description

N

B

Output 0 (least significant bit)

N+1

B

Output 1

N+2

B

Output 2

N+3

B

Output 3

N+4

B

Output 4

N+5

B

Output 5

N+6

B

Output 6

N+7

B

Output 7 (most significant bit)

 

 

 

Specifications:

Spec

Tune

Default

Type

Range

Description

S1

N

5

I

Note 1

Block address of selected input

S2

N

0

I

0 - 2

Conversion mode:

0 = select (unlimited number of blocks in link list)

1 = integer (maximum of 4 blocks in link list)

2 = BCD (maximum of 4 blocks in link list)

S3

N

0

I

Note 1

Block address of next block in link list

 

 

 

126.1   Explanation

 

126.1.1  Select Mode

 

In the select mode, the block output is all zeros and a one in the position specified by the real input. For example, if the real input is a seven, the eighth boolean output is a one and all others are zeros. In this mode, an unlimited number of real signal demultiplexer blocks can be linked together. If <S1> is less than zero, output zero equals one. If <S1> is greater than the maximum, the last output is set. If a number outside of the available range (for example, zero through seven in the case of a master) is selected, the nearest output is set. For example, if the number selected is -1, the zero output changes to a one.

 

126.1.2  Integer Mode

 

The integer mode converts the real input to a binary bit pattern. For example, if the input is 135, the binary output is 1000111, since 135+128+4+2+1. The least significant digit is output zero of the master block. This is true no matter how many blocks are in the link list. Table 126-1 shows the integer mode input to output relationship.

Up to four real signal demultiplexer blocks can be linked together in the integer mode, allowing the conversion of any real number up to 4.2 x 109 to binary digits.

 

                        

 

 

126.1.3  BCD Mode

 

The BCD mode converts the real input to BCD digits. Each digit of the real number converts to four boolean digits by writing the real digit as the sum of the first four powers of two (eight, four, two, one). For example, if the real digit is a six, the boolean outputs for that digit are 0110 since 6+0(8)+1(4)+1(2)+0(1). Table 126-2 shows how each group of outputs represents two real digits.

 

Up to four real signal demultiplexer blocks can be linked together in the BCD mode allowing for the conversion of any real number up to eight digits in length. The least significant digit is always represented by outputs zero through three of the master block, no matter how many blocks are linked in series. Figure 126-2 and Table 126-3 show this arrangement. Table 126-3 shows sample outputs for each of the three modes. There are two blocks in the link list. Outputs zero through seven are from the group master, and outputs eight through 15 are from the second block.

 

                         

 

 

 

 

 

                             

 

 

126.2   Applications

 

Real signal demultiplexer blocks can be used for a variety of control purposes. Figure 126-2 shows how, in the select mode, the boolean outputs can be used to trigger execution of auxiliary logic sequences in a batch process.

 

In the select mode, the real signal demultiplexer block converts the real step number input from the sequence generator block into a series of boolean outputs. The boolean outputs act as triggers for the auxiliary logics associated with the sequence. A value of one is output as the trigger for the auxiliary logic associated with the current step, initiating the execution of that logic.